In the field of semiconductor integrated circuits, the large scale integration of such circuits has made progress as a result of the miniaturization of the elements. When the elements are miniaturized, it is not merely the case that the operational speed of the elements increases, but the number of elements which can be placed on a single chip increases, so that the functions per chip can be increased. A good example of this is microprocessor LSI; in current leading edge microprocessor chips, the element dimensions are on the level of 0.5 microns, and the number of elements per chip reaches as high as several million. The cache memory and floating point decimal calculation unit and the like, which were conventionally placed on a separate chip from the microprocessor chip, have become able to be placed simultaneously on one microprocessor chip, since the circuit components themselves have become smaller as a result of the miniaturization of the elements, and this has played a great role in the improvement of computer performance.
However, in concert with the miniaturization of the elements and large scale integration, a number of problems have become apparent. One such problem is the hot carrier problem, in which, since a fixed power source voltage is applied to the minute elements, a strong electric field is generated within the elements, the accelerated carriers become hot carriers, and are injected into the gate oxide film, and the element characteristics tend to worsen. Furthermore, problems are also presented by difficulties in the layout and formation of wiring which is necessary to connect elements among the several million elements on a single chip. As a result of such problems, the present state is such that further miniaturization of the elements has become extremely difficult. Accordingly, there is little prospect for an improvement in the functions of the LSI chips in the future.
Such problems were solved by the invention of the neuron MOS transistor and logical circuits employing such neuron MOS transistors (inventors: Tadashi Shibata, Tadahiro Ohmi, Japanese Patent Application, First Publication, No. Hei 3-6679, and Japanese Patent Application No. Hei 3-83152). The neuron MOS transistor is a highly functional element possessing functions similar to those of a living nerve cell; it has a floating gate and a plurality of input coupling electrodes which are capacitively coupled with this floating gate, calculates a weighted average of the input signals from the plurality of input coupling electrodes at the floating gate level, and based on the results, the ON and OFF state of the transistor is controlled. In contrast to conventional transistors, which are termed 3 terminal devices in that the ON and OFF state of the current flowing between two terminals is controlled by means of a third terminal, the neuron MOS transistor is termed a 4 terminal device, in that a plurality of fourth terminals are provided, which are capable of controlling the method of control of the third terminal, which controls the ON and OFF state of the current flowing between two other terminals. Because the function of the element itself is high, if such an element is employed in a logic circuit, the number of elements or wirings necessary to realize a certain logical function is dramatically smaller than that in the case in which conventional CMOS logical circuits are employed. Furthermore, flexible signal processing, which is very difficult to achieve with circuits employing conventional transistors, in which a simple determination is made as to whether one input has a value of 0 or 1, and the ON and OFF state of the transistor is thus controlled, can be realized in a simple manner, and it is easily possible to construct flexible logical circuits, real-time rule-variable matching circuits, winner take all circuits, and circuits having high functions such as associative memory or the like. Furthermore, it is also a simple matter to realize functions which extract characteristics from a very large amount of data, and using such functions, a simplification and increase in speed of circuits is also expected even in the field of image data processing, such as letter recognition, or the detection of movement vectors in images or the like. In this way, the neuron MOS transistor is a completely new device having a possibility of giving rise to completely novel circuit technologies in the realm of ultra high speed and ultra high function LSI realization.
However, since the neuron MOS transistor has a floating gate, it has the following serious problems with respect to reliability. The neuron MOS transistor handles multivalent voltage signals at the floating gate level. That is to say, the difference in potential between the ground potential (GND) and the power source voltage (V.sub.DD) is allocated so as to be divided among a plurality of logical levels, and threshold operations are conducted. If the power source voltage is considered to be fixed, then the difference in voltage between a certain logical level and nearby logical levels, that is to say, the logical swing, becomes smaller as the number of multivalent levels becomes larger, and this leads to an undesirable reduction in the noise margin. Accordingly, in circuitry employing neuron MOS transistors, errors in the threshold value of the transistors must be controlled so as to be sufficiently small in comparison with a binary logic circuit in order to prevent mistakes in the operation of the circuitry.
However, as a result of the variation in the amount of charge present in the floating gates, the error in the threshold values of neuron MOS transistors is in all probability greater than the error in the threshold values of common MOS transistors. Table 1 shows the threshold values in 9 neuron MOS transistors on a single wafer immediately after the manufacture thereof, as seen from the input coupling electrodes. In fact, the variation encompasses a range of 9V, from -7.95V to +1.02V. Since the variation in the threshold values of common MOS transistors is approximately 0.2V, this represents a variation which is 45 times greater than that in common MOS transistors. The charge which is injected into the floating gate of a MOS transistor does not dissipate of its own accord, as a result of the extremely high insulating resistance, but remains unchanged, and exerts a direct influence on the threshold value. The large variation in the threshold value of neuron MOS can be traced to irregularities within the wafer surface during the manufacturing process of the device, such as reactive ion etching or sputtering or the like, and this variation results from the charge, irregular from device to device, which remains in the floating gate.
TABLE 1 ______________________________________ Transistor Number Threshold Value (V) ______________________________________ 1# 1.017 2# 0.259 3# 0.081 4# -1.962 5# -3.193 6# -3.716 7# -4.602 8# -7.209 9# -7.949 ______________________________________
However, the initial variation in the threshold values after the production of the devices can be eliminated to a certain extent by means of a procedure of ultraviolet (UV) irradiation or the like. Table 2 shows the threshold values after the irradiation with UV light for a period of 1,000 seconds of the devices having varying threshold values after the manufacturing processes thereof which were shown in Table 1. The variation is reduced to 0.17V. However, even at this level, this is insufficient for neuron MOS transistors handling multivalent signals, and thus the number of multivalent levels which can be handled by the neuron MOS transistor are dramatically restricted.
TABLE 2 ______________________________________ Transistor Number Threshold Value (V) ______________________________________ 1# 2.205 2# 2.118 3# 2.056 4# 2.219 5# 2.150 6# 2.078 7# 2.225 8# 2.164 9# 2.058 ______________________________________
Furthermore, what is critical with respect to the neuron MOS transistor is the change over time in the threshold value which occurs simultaneously with the operation of the device. This occurs primarily as a result of the injection of hot carriers into the floating gate. In standard MOS transistors, almost all of the hot carriers injected into the gate oxide film pass through this gate oxide film and escape to the gate electrodes, so that the amount of charge which is captured within the oxide film and thus alters the threshold value is only a very small part of the total amount of charge injected. However, in the neuron MOS, almost all of the injected charge remains within the floating gate, so that even with a very small amount of injected charge, the threshold value of the neuron MOS transistor changes dramatically. It is thus not merely the case that the neuron MOS transistor has an allowable error margin in the threshold values which is smaller than that of the standard MOS transistor, but also the amount of change in the threshold value as a result of hot carrier injection is much larger.
The floating gate type EPROM, which has a floating gate in the same way as the neuron MOS transistor, is a device which simply determines binary values of 0 or 1, and the allowable change over time in the threshold value thereof is large (on the level of several volts). Accordingly, it is possible to ensure the data maintenance characteristics over a number of years, and such devices have been placed into practical application. In contrast, the neuron MOS transistor is a device which handles multivalent signals at the floating gate, as described above, the allowable change in the threshold values is small, and errors in operation are likely to be caused as a result of even small amounts of charge injection.
As described above, although the neuron MOS transistor is highly functional, it has a large defect in that the reliability thereof is extremely poor. Furthermore, in order to take advantage of the high functionality of the device, it is necessary to increase the number of inputs of the neuron MOS transistor; however, as the number of inputs increases, the logical swing is reduced, and the reliability is further worsened, so that it has not been a simple matter to increase the number of inputs.
The present invention has as an object thereof to provide a highly functional semiconductor integrated circuit employing this neuron MOS transistor, in which a switch is added to the floating gate of the neuron MOS transistor, and the charge remaining in the floating gate or injected into the floating gate is rapidly eliminated via this switch, and thereby, the reliability of the neuron MOS transistor is improved, so that it becomes possible to make use of a neuron MOS having a large number of simultaneous inputs.